HPCA’14 Tutorial: OpenSPL and Computing in 2D Space

Jacob Bower

Oskar Mencer

Veljko Milutinovic

Zivojin Sustran

Maxeler Technologies

University of Belgrade

Time: Saturday 15th February 2014, 9am – 12.30pm (approx.)


As the number of on-die transistors continues to grow, new computing models are needed to utilize this growing compute capacity despite a clock-frequency scaling wall, and relatively sluggish improvements in I/O bandwidth. The spatial compute and programming model, as introduced by the OpenSPL [1]  specification, provides a method for taking advantage of compute capacity offered by current and trending hardware technology. With spatial computing, compute processing units are laid out in space (either physically or conceptually) and connected by flows of data. The result of this approach is compute implementations which are naturally highly-parallel and thus very effectively use modern transistor-rich hardware.

In this tutorial, we describe both the spatial computing model and a practical realization of the OpenSPL specification which embodies this targeting Multiscale Dataflow Engines. Multiscale Dataflow Engines are a platform which directly implement the spatial computing model in hardware while at the same time supporting tight integration with conventional CPU-based compute resources [2]. We present technical details of how to implement computational algorithms via the OpenSPL specification and how these operate on Multiscale Dataflow Engine hardware.

[1] www.openspl.org

[2] M. J. Flynn, O. Mencer, V. Milutinovic, G. Rakocevic, P. Stenstrom, R. Trobec, M. Valero: “Moving from Petaflops to Petadata”, Communications of the ACM, May 2013

Target Audience

This tutorial is aimed at a technical audience interested in using cutting-edge technology to build extremely high-throughput/low-latency data-processing solutions. A software background and/or domain-specific computational goals e.g. engineers scientists, etc., will help to get the most out of this talk.

Tentative Talk Outline

  • Spatial computing and OpenSPL
  • Dataflow Computing platform
  • MaxCompiler and related tools for programming Dataflow Engines
  • Using SLiC Interface for software integration of Dataflow Engines
  • Example applications and performance numbers
  • MaxCompiler/OpenSPL programming constructs
  • Developing, building, and running a Dataflow Engine design with MaxIDE

Author Biographies

Jacob Bower (speaking)

Jacob Bower is currently responsible for Maxeler application projects at the company’s Palo Alto, CA office. In his previous role at Maxeler, Jacob was Head of Software during which he lead development of Maxeler’s compiler technology and related software tools. Prior to working at Maxeler, Jacob held positions at IBM, Xilinx, and as a researcher at Imperial College London. Jacob has an MEng in Computing from Imperial College London.

Oskar Mencer

Prior to founding Maxeler, Oskar was Member of Technical Staff at the Computing Sciences Center at Bell Labs in Murray Hill, leading the effort in “Stream Computing”. He joined Bell Labs after receiving a PhD from Stanford University. Besides driving Maximum Performance Computing (MPC) at Maxeler, Oskar was Consulting Professor in Geophysics at Stanford University and he is also affiliated with the Computing Department at Imperial College London, having received two Best Paper Awards, an Imperial College Research Excellence Award in 2007 and a Special Award from Com.sult in 2012 for “revolutionising the world of computers”.

Veljko M. Milutinovic

Dr. Veljko Milutinovic is a professor at the School of Electrical Engineering, University of Belgrade, Serbia. During the 80′s, for about a decade, he was on the faculty of Purdue University in the U.S.A, where he co-authored the architecture and design of the world’s first DARPA GaAs microprocessor. During the 90′s, after returning to Serbia, he took part in teaching and research at a number of major EU schools. He also delivered lectures at Stanford and MIT, and has about 20 books published by leading publishers in the U.S.A. Dr. Milutinovic is a Fellow of the IEEE and a Member of Academia Europaea.

Zivojin Sustran

Zivojin Sustran is a teaching assistant and PhD candidate at the School of Electrical Engineering, University of Belgrade, Serbia. He received his BSc (second highest GPA in the year level) and MS (highest GPA in the year level) in Computer Engineering. His current research interests include Computer Architecture and VLSI. He is the teaching assistant for the course on processor design and Maxeler Dataflow computing.