Oskar Mencer, CEO of Maxeler, is to present a CRS4 colloquium titled “Delivering the next generation of supercomputing with reconfigurable hardware” in Cagliari, Sardinia, June 6.
As microprocessors reach the limits of attainable clock frequencies and acceptable power consumption, major microprocessor vendors are enabling higher degrees of parallelism by increasing the number of cores per chip. The resulting increased complexity in harnessing the extra compute resource presents a considerable challenge to the business community.
Many important applications, in fields as diverse as earth science and finance, exhibit significantly worse than linear scaling on multiple cores as they encounter the memory wall. This situation is only likely to get worse as the major microprocessor vendors move beyond quad/six-core chips to many-core architectures (GPUs). At the same time, programmers must now grapple with an even more complex programming model of parallelism at the core, chip, node and cluster level.
Maxeler’s dataflow computing solution based on Field-Programmable Gate Array (FPGA) accelerators offers a way to avoid the memory and power walls. By mapping compute-intensive algorithms directly into parallel FPGA hardware and tightly coupled to a CPU through a high-speed I/O bus, conventional CPU applications can be accelerated by orders of magnitude or more. At Maxeler we are bridging the gap between research and production quality systems, delivering complete HPC application solutions utilizing reconfigurable dataflow engines.