Maxeler Chairman Michael J Flynn delivers keynote at IPDPS

Regardless of the number or speed of processors, performance is limited by the supply of data from memory. This depends on the access time to memory and thus on wire delay which remains constant with scaling.

One solution to this memory wall is an architectural arrangement to stream data across multiple processing elements before storing the result in memory. This MISD type of configuration provides multiple operations per data item fetched from memory.

One realization of this streamed approach uses FPGAs. Prof. Flynn will be discussing both the general memory problem and some results based on work at Maxeler with the MAX-1 FPGA acceleration platform at the IEEE International Parallel & Distributed Processing Symposium in California on March 28th 2007.

IPDPS is an international forum for engineers and scientists from around the world to present their latest research findings in all aspects of parallel computation. In addition to technical sessions of submitted paper presentations, the meeting offers workshops, tutorials, and commercial presentations & exhibits.

Prof. Michael J. Flynn is Chairman of Maxeler Technologies and Professor of Electrical Engineering at Stanford University.