With microprocessors having hit the limits of attainable clock frequencies and acceptable power consumption, we have reached a significant inflection point in the high performance computing environment.

Future significant improvements in performance must come from exploiting parallelism. Recognizing this, Intel and AMD are rapidly scaling up the number of cores per chip and processors per node in search of greater speed. However, regardless of the number or speed of processors, performance is limited by the supply of data from memory. This depends on the access time to memory and thus on wire delay which remains constant with scaling.

Maxeler Technologies’ Chairman Michael J Flynn will be talking about the parallel processing future and the pitfalls therein at the 14th IEEE International Conference on High Performance Computing (HiPC) in Goa, India, December 18-21, 2007.

The IEEE International Conference on High Performance Computing (HiPC 2007), to be held in Goa, India, during December 18-21, 2007, is a forum for presentation of current work by researchers in the field of High Performance Computing from around the world as well as to highlight activities in Asia.

Prof. Michael J. Flynn is Chairman of Maxeler Technologies and Professor of Electrical Engineering at Stanford University.