Maxeler Technologies’ latest work on acceleration of seismic processing using FPGAs will be presented at the 70th Annual Meeting of the European Association of Geoscientists and Engineers in Rome.
EAGE is one of the premier geoscience conferences in the world, attracting over 300 exhibiting companies. This year’s conference theme is “Leveraging Technology”, reflecting and highlighting the need for innovation and continuous technological development to meet new challenges and new requirements.
Two poster papers being presented at this year’s EAGE showcase Maxeler’s work on FPGA acceleration of seismic processing.
Seismic modeling and data processing moves terabytes of data for each project and the potential of FPGAs as stream processor accelerators are very attractive for this problem. Many factors need to be considered when implementing a software code on a reconfigurable substrate such as an FPGA. Of course, optimal software implementation of the target algorithm may not be the ideal input to be mapped onto FPGA circuits. Therefore, one of the first steps for an FPGA implementation is to evaluate the input algorithm from the design standpoint to understand the compute capability, memory capacity and memory bandwidth tradeoffs involved in implementing the original equations in different ways. In Design Space Analysis for the Acoustic Wave Equation Implementation on FPGA Circuits, presented by Maxeler and Chevron ETC, we illustrate these tradeoffs with an analysis of the design space for acoustic wave equation modeling.
Accelerating Seismic Computations on FPGAs – from the Perspective of Number Representations presents the latest work from the collaboration between Maxeler and the Stanford Center for Earth and Environmental Sciences (CEES). The paper shows that using reduced arithmetic precision can produce equivalent results within acceptable tolerances, compared to conventional floating point arithmetic. Using FPGAs with hardware support for reconfigurable number formats and custom bitwidths, reduced precision greatly decreases the area cost and I/O bandwidth of the design, thus multiplying the performance with concurrent processing cores on an FPGA.
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