Oskar Mencer, CEO of Maxeler, presents talk at Barcelona Supercomputing Center (BSC) titled “Programming dataflow engines for HPC applications”.

Microprocessors have been hitting the limits of attainable clock frequencies for the past few years, resulting in the current multi-core processor solutions provided by the major microprocessor vendors. Many important applications in fields as diverse as earth science and finance exhibit significantly worse than linear scaling on multiple cores, a problem that is only going to worsen as the major microprocessor vendors move beyond quad/six-core chips to many-core architectures.

At the same time, programmers must now grapple with an even more complex programming model of parallelism at the core, chip, node and cluster level. Dataflow compute engines can offer a way to avoid the memory and power walls and simplify the parallelism model, and can be implemented efficiently on modern FPGA platforms.

However FPGA accelerators have traditionally been thought of as hard to program and use. In this talk we present our dataflow programming system called MaxCompiler, discuss how common operations map to a dataflow programming model and show how complete dataflow accelerated applications can be coded quickly by scientific programmers without needing specific FPGA expertise.