At the recent EE380 seminar at Stanford, Mike Flynn gave a comprehensive presentation examining the broad use of accelerator assistance to multicore processing compared to the specialized processing performed by FPGAs.

Mike discussed how the FPGA array technology wins out on performance for most relevant applications and explained that using Maxeler’s FPGA compiler toolkit, it is now feasible to transform a software application into a data flow graph mapped to an unconstrained systolic array. This allows the array structure to be matched to the applications structure without the constraint to nearest neighbor communications.

Detailed examples show a forward modeling implementation for seismic data processing, realizing a 2000 node systolic array on 2 FPGAs, each node performing an operation every 4ns, resulting in a speedup of over 200x compared to an Intel CPU.