The emphasis on multi core architectures and multi node parallel processors comes about, in part, from the failure of frequency scaling not because of breakthroughs in parallel programming or architecture.

Progress in automatic compilation of serial programs into multi tasked ones has been slow. The standard approach to programming HPC is to implement an application on as many multi core processors as possible, up to a point of memory saturation; after which partitioning continues over multiple such nodes. Now the inter node communications reduces the computational efficiency and scales up cost, power, cooling requirements and reliability concerns.

At ISPDC 2008 in Poland on July 1-5, Maxeler Technologies’ Chairman Michael J Flynn will be presenting Maxeler’s alternative model which stresses maximizing the node speedup as far as possible before considering multi node partitioning. Node speedup starts with the use of an accelerator adjunct to the computational node and then uses a cylindrical rather than layered programming model to ensure application speedup.