MAX-UP Publications

MAX-UP members frequently publish research work with Maxeler technology. On this page we highlight a few of these publications. If you would like your MAX-UP publication considered for inclusion here, please contact Cliff Winckless.

2023

High-Level Synthesis versus Hardware Construction

Alexander Kamkin, Mikhail Chupilko, Mikhail Lebedev, Sergey Smolov, Georgi Gaydadjiev§

ISP RAS Plekhanov RUE, Russia §University of Groningen, Netherlands

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023

2021

Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor Neurons

Masashi Ogaki, Yukinori Sato

Toyohashi University of Technology, Toyohashi, Japan

International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 109-116, 2021

Reconfigurable Acceleration of Short Read Mapping with Biological Consideration

Ho-Cheung Ng, Izaak Coleman§, Shuanglong Liu* and Wayne Luk

Imperial College London, UK §Columbia University, USA *Hunan Normal University, China

International Symposium on Field-Programmable Gate Arrays (FPGA), 2021

2020

Acceleration of Short Read Alignment with Runtime Reconfiguration

Ho-Cheung Ng et.al.

Imperial College London, London, UK

Field-Programmable Technology (FPT) 2020

High performance reconfigurable computing for numerical simulation and deep learning

L. Gan, M. Yuan§, J. Yang*, et al.

Tsinghua University, Beijing, China §Jiangnan University, Jiangsu, China *Imperial College London, London, UK

CCF Transactions on High Performance Computing 2:196–208 (2020)

A CGRA Definition Framework for Dataflow Applications

G. Charitopoulos and D.N. Pnevmatikatos§

Technical University of Crete, Greece §National Technical University of Athens, Greece

Applied Reconfigurable Computing (ARC), 2020

Enabling Dynamic System Integration on Maxeler HLS Platforms

C. Kritikakis and D. Koch

The University of Manchester, Manchster, UK

Journal of Signal Processing Systems 92:887–905 (2020)

2019

Time-SWAD: A Dataflow Engine for Time-based Single Window Stream Aggregation

P. Geethakumari, V. Gulisano, P. Trancoso, and I. Sourdis

Chalmers University of Technology, Sweden

Field Programmable Technology (FPT), 2019

Porting ESCAPE Cloud Microphysics Dwarf to an FPGA

J. Targett, M. Lange§, and O. Marsden§

Imperial College London, UK §ECMWF, UK

The Platform for Advanced Scientific Computing (PASC) Conference, 2019

Field-Programmable Gate Arrays and Quantum Monte Carlo: Power Efficient Co-processing for Scalable High-Performance Computing

Salvatore Cardamone, Jonathan R. Kimmitt, Hugh G. A. Burton, and Alex J. W. Thom

University of Cambridge, Cambridge, UK

Int J Quantum Chem. 2019. 119:e25853.

Exploring the DataFlow Supercomputing Paradigm

Veljko Milutinovic and Milos Kotlar§

Indiana University, USA §University of Belgrade, Serbia

Springer ISBN 978-3-030-13803-5, 2019

Scalable Filtering Modules for Database Acceleration on FPGAs

Kristiyan Manev, Anuj Vaishnav, Charalampos Kritikakis, and Dirk Koch

University of Manchester, UK

International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), 2019

Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach

D. Masouros, K. Koliogeorgi, G. Zervakis, A. Kosvyra§, A. Chytas§, S. Xydis, I. Chouvarda§, D. Soudris

National Technical University of Athens, Greece §Aristotle University of Thessaloniki, Greece

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, pp. 622-625.

End-to-end Dynamic Stream Processing on Maxeler HLS Platforms

Charalampos Kritikakis and Dirk Koch

University of Manchester, UK

International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019

Designing and building application-centric parallel memories

Giulio Stramondo, Catalin Bogdan Ciobanu, Cees de Laat, and Ana Lucia Varbanescu

University of Amsterdam, The Netherlands

Concurrency and Computation: Practice and Experience, 2019;e5485.

Customisable Control Policy Learning for Robotics

Ce Guo, Wayne Luk, Stanley Qing Shui Loh, Alexander Warren§, Joshua Levine§

Imperial College London, UK §Intel Corporation, UK

International Conference on Application-specific Systems, Architectures and Processors (ASAP), Pages: 91-98, 2019

2018

Fast Sampling from Wiener Posteriors for Image Data with Dataflow Engines

Niall Jeffrey, Alan F. Heavens, Philip D. Fortio

Imperial College London, London, UK

Astronomy and Computing, Volume 25, Pages 230-237, ISSN 2213-1337, 2018

The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case

Harry Sidiropoulos, George Chatzikonstantis, Dimitrios Soudris, Christos Strydis§

ICCS, Greece §Erasmus University Medical Center Rotterdam, The Netherlands

Design and Architectures for Signal and Image Processing (DASIP), Porto, 2018, pp. 70-75.

Kalman Filter track reconstruction on FPGAs for acceleration of the High Level Trigger of the CMS experiment at the HL-LHC

Sioni Summers and Andrew Rose

Imperial College London, UK

23rd International Conference on Computing in High Energy and Nuclear Physics (CHEP 2018)

Lattice-based Scheduling for Multi-FPGA Systems

Teng Yu*, Bo Feng, Mark Stillwell, Liucheng Guo, Yuchun Ma, John Thomson*

*University of St Andrews, UK Imperial College London, UK Tsinghua University, China

International Conference on Field-Programmable Technology (FPT), 2018

Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA

Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk and Xinyu Niu

Imperial College London, UK Corerain Technologies Ltd, Shenzhen, China

Field Programmable Logic and Applications (FPL) 2018

CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems

Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, and Mark Salmon

Imperial College London, UK Cambridge University, UK

Field Programmable Logic and Applications (FPL) 2018

DARSA: A dataflow analysis tool for reconfigurable platforms

George Charitopoulos and Dionisios N. Pnevmatikatos

Technical University of Crete, Greece

SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018

A performance evaluation of multi-FPGA architectures for computations of information transfer

Konstantinos Iordanou, Sofia Maria Nikolakaki§, Pavlos Malakonakis, Apostolos Dollas

Technical University of Crete, Greece §Boston University, USA

SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018

EXTRA: An Open Platform for Reconfigurable Architectures

Catalin Bogdan Ciobanu et.al.

SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018

The VINEYARD integrated framework for hardware accelerators in the cloud

C. Kachris, D. Soudris, S. Mavridis§, M. Pavlidakis§, C. Symeonidou§, C. Kozanitis§, A. Bilas§, D. Fenacci*, S. V. Bogaraju*, H. Vandierendonck*, D. S. Nikolopoulos*

ICCS, Greece §FORTH, Greece *Queen’s University Belfast, UK

SAMOS: Int Conf Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018

MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs

Catalin Bogdan Ciobanu, Giulio Stramondo, Cees de Laat, and Ana Lucia Varbanescu

University of Amsterdam, The Netherlands

IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS) 2018: 107-114.

Towards Application-Centric Parallel Memories

Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, and Cees de Laat

University of Amsterdam, The Netherlands

Euro-Par 2018: Parallel Processing Workshops, LNCS, vol 11339. Springer, 2018

OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels

Francesco Peverelli, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio

Politecnico di Milano, Milan, Italy

IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS) 2018: 91-98.

Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform

Chaim Baskin, Evgenii Zheltonozhskii, Alex M. Bronstein, Avi Mendelson, Natan Liss

Technion – Israel Institute of Technology, Haifa, Israel

IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS) 2018: 162-169.

Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control

Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau, Alexander Warren and Ben Jeppesen

Imperial College London, UK Intel, UK

International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018

From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations

Francis P. Russell, James Stanley Targett, and Wayne Luk

Imperial College London, UK

International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018

A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes

Achim Lösch, Marco Platzner

Paderborn University, Paderborn, Germany

International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018

HLS Enabled Partially Reconfigurable Module Implementation

N.B. Grigore, C. Kritikakis, D. Koch

The University of Manchester, Manchester, UK

Architecture of Computing Systems (ARCS) LNCS, vol 10793. Springer, 2018

Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes

A. Lösch, A. Wiens, M. Platzner

Paderborn University, Paderborn, Germany

Architecture of Computing Systems (ARCS) LNCS, vol 10793. Springer, 2018

CJS: Custom Jacobi Solver

Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, and Mark Salmon

Imperial College London, UK Cambridge University, UK

International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) 2018

Data-flow Conjugate Gradient Solver for Lattice QCD Calculations on FPGA Accelerator

Thomas Janson and Udo Kebschull

Goethe University Frankfurt, Germany

DPG Conference, HK 42.6, Bochum, Germany, February 2018

2017

BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations

G. Smaragdos, G. Chatzikonstantis§, R. Kukreja$ , H. Sidiropoulos§, D. Rodopoulos**, I Sourdis*, Z. Al-Ars$, C. Kachris§, D. Soudris§, C. I De Zeeuw and C Strydis

Neuroscience department, Erasmus MC, Rotterdam, Netherlands * Computer Science and Eng. department, Chalmers University of Technology, Gothenburg, Sweden § MicroLab, National Technical University of Athens, Athens, Greece $ Computer Eng. Lab, Delft University of Technology, Delft, Netherlands ** imec, Leuven, Belgium

Journal of Neural Engineering, vol. 14, No 6, IOP Publishing (2017).

FP-BNN: Binarized neural network on FPGA

Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk§, Shaojun Wei

Institute of Microelectronics, Tsinghua University, China, §Department of Computing, Imperial College London, UK

Neurocomputing, Volume 275, Pages 1072-1086. 2017.

A Fully-Pipelined Hardware Design for Gaussian Mixture Models

Conghui He, Haohuan Fu, Ce Guo, Wayne Luk and Guangwen Yang

IEEE Transactions on Computers, 66(11): 1837-1850 (2017)

Single window stream aggregation using reconfigurable hardware

P. Geethakumari, V. Gulisano, B. Svensson, P. Trancoso, and I. Sourdis

Chalmers University of Technology, Sweden

Field Programmable Technology (FPT), 2017

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project

Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo, Michael Hübner§, Andreas Brokalakis+, Catalin B. Ciobanu*, Dirk Stroobandt**, Marco D. Santambrogio

Politecnico di Milano, Italy, §Ruhr-Universität Bochum, Germany, *Universiteit van Amsterdam, Netherlands +Synelixis, Greece **Ghent University, Belgium

IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017: 368-373

Dataflow Acceleration of scikit-learn Gaussian Process Regression

Michail Doukas, Sotirios Xydis, Dimitrios Soudris

National Tech. University of Athens, Athens, Greece

Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM) 2017

Highly Parallel Lattice QCD Wilson Dirac Operator with FPGAs

Thomas Janson and Udo Kebschull

Goethe University Frankfurt, Germany

Advances in Parallel Computing (ParCo2017), Vol. 32,Pages 664-672, 2017

Efficient Branch and Bound on FPGAs using Work Stealing and Instance-Specific Designs

H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl

University of Paderborn

ACM Trans. on Reconfigurable Technology and Systems (TRETS). 2017.

2016

Optimising Sparse Matrix Vector Multiplication for Large Scale FEM problems on FPGA

Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer Sherwin§

Department of Computing, Imperial College London, §Department of Aeronautics, Imperial College London

2016 International Conference on Field Programmable Logic and Applications (FPL)

F-CNN: An FPGA-based Framework for Training Convolutional Neural Networks

Wenlai Zhao§, Haohuan Fu§, Wayne Luk, Teng Yu, Shaojun Wang*, Bo Feng§, Yuchun Ma§ and Guangwen Yang§

Imperial College London, UK, §Tsinghua University, China, *Harbin Institute of Technology, China

International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016

Relation-Oriented Resource Allocation for Multi-Accelerator Systems

Teng Yu, Bo Feng§, Mark Stillwell*, Jose Gabriel F Coutinho, Wenlai Zhao§, Shuang Liang§, Wayne Luk, Alexander L. Wolf, Yuchun Ma§

Imperial College London, UK, §Tsinghua University, China, *Cisco Meraki, UK

International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016

A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification

Shaojun Wang§, Xinyu Niu§, Ning Ma, Wayne Luk§, Philip Leong*, and Yu Peng

Harbin Institute of Technology, China, §Imperial College London, UK, *University of Sydney, Australia

Applied Reconfigurable Computing (ARC), Springer, LNCS, Volume 9625, pp 105-116, 2016

Leveraging FPGAs for Accelerating Short Read Alignment

James Arram, Thomas Kaplan, Wayne Luk and Peiyong Jiang§

Department of Computing, Imperial College London, §Department of Chemical Pathology, The Chinese University of Hong Kong

IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol.PP, no.99, pp.1-1, 2016

Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs

Maciej Kurek, Marc Peter Deisenroth, Wayne Luk and Timothy Todman

Imperial College London

2016 International Symposium on Field-Programmable Custom Computing Machines (FCCM)

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center

Achim Lösch, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner

University of Paderborn

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016

Performance Analysis of Accelerated Biophysically-Meaningful Neuron Simulations

Georgios Smaragdos, Georgios Chatzikostantis§, Sofia Nomikou§, Dimitrios Rodopoulos§, Ioannis Sourdis*, Dimitrios Soudris§, Chris I. De Zeeuw and Christos Strydis

Erasmus Medical Center, Netherlands, §National Technical University of Athens, Greece, *Chalmers University of Technology, Sweden

International Symposium on Performance Analysis of Systems and Software ISPASS 2016, April 2016 – Nominated for Best Paper Award

GraphOps: A Dataflow Library for Graph Analytics Acceleration

Tayo Oguntebi, Kunle Olukotun

Stanford University

International Symposium on Field-Programmable Gate Arrays (FPGA), pp 111-117, 2016

CASK – Open-Source Custom Architectures for Sparse Kernels

Paul Grigoras, Pavel Burovskiy and Wayne Luk

Department of Computing, Imperial College London, UK

International Symposium on Field-Programmable Gate Arrays (FPGA), pp 179-184, 2016

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

Kit Cheung†§, Simon R. Schultz§ and Wayne Luk

Custom Computing Research Group, Department of Computing, Imperial College London, §Centre for Neurotechnology, Department of Bioengineering, Imperial College London

Frontiers in Neuroscience, vol 9, no 00516, 2016

Spiking neural network simulation on FPGAs with automatic and intensive pipelining

Taro Kawao, Masato Neishi, Tomohiro Okamoto, Amir Masoud Gharehbaghi, Takashi Kohno, and Masahiro Fujita

University of Tokyo, Japan

International Symposium on Nonlinear Theory and Its Applications, NOLTA 2016

Leveraging Reconfigurable Computing in Distributed Real-time Computation Systems

A. Nydriotis, P. Malakonakis, N. Pavlakis, G. Chrysos, E. Ioannou, E. Sotiriades, M. Garofalakis and A. Dollas

Technical University of Crete, Greece

EDBT/ICDT Workshops, 2016

2015

Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

Tobias Kenter, Henning Schmitz, and Christian Plessl

University of Paderborn

International Journal of Reconfigurable Computing, Volume 2015 (2015), Article ID 859425

On the use of programmable hardware and reduced numerical precision in earth-system modeling

Peter D. Düben, Francis P. Russell§, Xinyu Niu§, Wayne Luk§ and T. N. Palmer

Department of Physics, University of Oxford, §Department of Computing, Imperial College London

Journal of Advances in Modeling Earth Systems, vol. 7, issue 3, pp. 1393-1408, 2015.

Using Type Transformations to Generate Program Variants for FPGA Design Space Exploration

Syed Waqar Nabi and Wim Vanderbauwhede

University of Glasgow

ReConFigurable Computing and FPGAs (ReConFig), 2015

FPGA Port of a Large Scientific Model from Legacy Code: The Emanuel Convection Scheme

Kristian Thorin Hentschel, Wim Vanderbauwhede, Syed Waqar Nabi

University of Glasgow

Advances in Parallel Computing, Volume 27, Pages 469 – 478

FPGA Acceleration of Reference-Based Compression for Genomic Data

James Arram, Moritz Pflanzer, Thomas Kaplan, Wayne Luk

Department of Computing, Imperial College London

Field Programmable Technology (FPT), pp. 9-16., 2015

Efficient Assembly for High Order Unstructured FEM Meshes

Pavel Burovskiy, Paul Grigoras, Spencer Sherwin§, Wayne Luk

Department of Computing, Imperial College London, §Department of Aeronautics, Imperial College London

2015 International Conference on Field Programmable Logic and Applications (FPL)

Feasibility Study of Porting a Particle Transport Code to FPGA

Iakovos Panourgias, Michele Weiland, Mark Parsons, David Turland§, Dave Barrett§, Wayne Gaudin§

EPCC, University of Edinburgh, §AWE

High Performance Computing, Lecture Notes in Computer Science, Springer, vol 9137, pp 139-154, 2015

Paradigm Shift in Big Data SuperComputing: DataFlow vs. ControlFlow

Nemanja Trifunovic, Veljko Milutinovic, Jakob Salom§ and Anton Kos*

University of Belgrade, §Mathematical Institute of the Serbian Academy of Sciences and Arts, *University of Ljubljana

Journal of Big Data, May 2015

In-circuit temporal monitors for runtime verification of reconfigurable designs

Tim Todman, Stephan Stilkerich§ and Wayne Luk

Department of Computing, Imperial College London, UK, §Airbus Group Innovations, Ottobrun

Design Automation Conference (DAC), 50:1-50:6, 2015

Reconfigurable acceleration of fitness evaluation in trading strategies

Andreea Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon

Department of Computing, Imperial College London,

Application-specific Systems, Architectures and Processors (ASAP), p. 210-217, 2015

Architectures and precision analysis for modelling atmospheric variables with chaotic behaviour

Francis P. Russell, Peter D. Düben§, Xinyu Niu, Wayne Luk, T. N. Palmer§

Imperial College London, §University of Oxford

2015 International Symposium on Field-Programmable Custom Computing Machines (FCCM)

Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment

James Arram, Wayne Luk, Peiyong Jiang§

Imperial College London, §Chinese University of Hong Kong

2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

Automating Elimination of Idle Functions by Runtime Reconfiguration

Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu§, Oliver Pell

Imperial College London, §Tianjin University, Maxeler Technologies

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 8 Issue 3, May 2015

Mapping adaptive particle filters to heterogeneous reconfigurable systems

T. C. P. Chow, X. Niu, A. Eele§, J. Maciejowski§, P.Y.K. Cheung and W. Luk

Imperial College London, §University of Cambridge

ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 4, Article 36, Jan 2015

2014

Pipelined HAC estimation engines for multivariate time series

C. Guo and W. Luk

Imperial College London

Journal of Signal Processing Systems, Volume 77, Issue 1-2, pp. 117-129, Oct 2014

Kernel-centric acceleration of high accuracy stereo-matching

Tobias Kenter, Henning Schmitz, Christian Plessl

University of Paderborn

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

Collaborative processing of Least-Square Monte Carlo for American options

Jinzhe Yang, Ce Guo§, Wayne Luk§, Terence Nahar

Aberdeen Asset Management, §Imperial College London

2014 International Conference on Field-Programmable Technology (FPT)

A Dataflow System for Anomaly Detection and Analysis

Andrei Bara, Xinyu Niu, Wayne Luk

Imperial College London

2014 International Conference on Field-Programmable Technology (FPT)

Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation

Jinzhe Yang§, Binghuan Lin*, Wayne Luk, Terence Nahar§

Imperial College London, §SWIP, *Techila Technologies

International Conference on Field Programmable Logic and Applications (FPL)

Patra: Parallel tree-reweighted message passing architecture

Wenlai Zhao, Haohuan Fu, Guangwen Yang, Wayne Luk§

Tsinghua University, §Imperial College London

International Conference on Field Programmable Logic and Applications (FPL)

Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era

João Andrade, Frederico Pratas§, Gabriel Falcão, Vítor Manuel Mendes da Silva, Leonel Sousa§

University of Coimbra, Portugal, §Universidade de Lisboa, Portugal

Application-specific Systems, Architectures and Processors (ASAP)

A Hybrid Genetic-Programming Swarm-Optimisation Approach for Examining the Nature and Stability of High Frequency Trading Strategies

Andreea-Ingrid Funie, Mark Salmon§, Wayne Luk

Imperial College London, §University of Cambridge

13th International Conference on Machine Learning and Applications, ICMLA 2014

Automating Optimization of Reconfigurable Designs

M. Kurek, T. Becker, T. C. P. Chau and W. Luk

Imperial College London

2014 International Symposium on Field-Programmable Custom Computing Machines (FCCM)

SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications

T. C. P. Chau, M. Kurek, J. S. Targett, J. Humphrey, G. Skouroupathis, A. Eele§, J. Maciejowski§, B. Cope*, K. Cobden*, P. Leong, P. Y. K. Cheung, W. Luk

Imperial College London, §University of Cambridge, *Altera, University of Sydney

2014 International Symposium on Field-Programmable Custom Computing Machines (FCCM)

Accelerating parameter estimation for multivariate self-exciting point processes

Ce Guo, Wayne Luk

Imperial College London

Field-Programmable Gate Arrays (FPGA) 2014: 181-184

Elastic Management of Reconfigurable Accelerators

Paul Grigoras, Max Tottenham, Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk

Imperial College London

International Symposium on Parallel and Distributed Processing with Applications

2013

Dynamic Stencil: Effective Exploitation of Run-time Resources in Reconfigurable Clusters

Xinyu Niu, Jose G. F. Coutinho, Wang Yu§ and Wayne Luk

Imperial College London, §Tsinghua University

2013 International Conference on Field-Programmable Technology (FPT), pp. 214-221

Hardware Acceleration of Genetic Sequence Alignment

J. Arram, K.H.Tsoi, W. Luk and P. Jiang§

Imperial College London, §Chinese University of Hong Kong

Reconfigurable Compitung: Architectures, Tools and Applications (ARC) 2013, pp 13-24

A Flexible Hashtable Design For 10Gbps Key-value Stores

Z. Istvan, G. Alonso, M. Blott§, K. Vissers§

ETH Zürich, §Xilinx Inc.

23rd International Conference on Field Programmable Logic and Applications (FPL’13)

A2B: An integrated framework for designing heterogeneous and reconfigurable systems

C. Pilato, R. Cattaneo, G. Durelli, A.A. Nacci, M.D. Santambrogio, D. Sciuto

Politecnico di Milano

NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2013

FASTER Run-Time Reconfiguration Management

C. Ciobanu§, D. Pnevmatikatos, K. Papadimitriou, G. Gaydadjiev§

§Chalmers University of Technology, Foundation for Research and Technology – Hellas

ICS ’13 Proceedings of the 27th international ACM conference on International conference on supercomputing

An FPGA-Based Data Flow Engine for Gaussian Copula Model

H. Ruan, X. Huang, H. Fu, G. Yang, W. Luk

Tsinghua University

Proceedings of the 21th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 218-225, Seattle, 2013.

A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications

G. Durelli, A.A. Nacci, R. Cattaneo, C. Pilato, D. Sciuto, M.D. Santambrogio

Politecnico di Milano

Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International

Accelerating Finite Difference Time Domain Simulation with Reconfigurable Dataflow Computers

H. Giefers§, C. Plessl, J. Förstner

§IBM Research, University of Paderborn

Fourth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

Dataflow Computing with Polymorphic Registers

C. Ciobanu§, G. Gaydadjiev§, C. Pilato, D. Sciuto

§Chalmers University of Technology, Politecnico di Milano

International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013

FPGA-accelerated Key Search for Cold-Boot Attacks against AES

H. Riebler, T. Kenter, C. Sorge, C. Plessl

University of Paderborn

International Conference on Field-Programmable Technology (ICFPT), 2013

A Heterogeneous Computing Framework for Computational Finance

Gordon Inggs, David B. Thomas, Wayne Luk

Imperial College London

42nd International Conference on Parallel Processing, ICPP 2013

Implementation of the RSA Algorithm on a Dataflow Architecture

N. Bezanic, J. Popovic-Bozovic, V. Milutinovic, I. Popovic

University of Belgrade

The IPSI BgD Transactions on Internet Research, IPSI Bgd Internet Research Society, Volume 9 Number 2 July 2013

Solving Gross Pitaevskii Equation Using Dataflow Paradigm

S. Stojanovic, D. Bojic, V. Milutinovic

University of Belgrade

The IPSI BgD Transactions on Internet Research, IPSI Bgd Internet Research Society, Volume 9 Number 2 July 2013

2012

A Fully-Pipelined Expectation-Maximization Engine for Gaussian Mixture Models

Ce Guo, Haohuan Fu§, Wayne Luk

Imperial College London, §Tsinghua University

2012 International Conference on Field-Programmable Technology (FPT)

Evaluating Reconfigurable Dataflow Computing Using the Himeno Benchmark

Y. Sato, Y. Inoguchi, W. Luk and T. Nakamura

JAIST, JST CREST, Imperial College London and Keio University

In Proc. 2012 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012

A mixed precision Monte Carlo methodology for reconfigurable accelerator systems

G.C.T. Chow, A.H.T. Tse, Q. Jin, W. Luk, P.H.W. Leong and D.B. Thomas.

Imperial College London

In Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), ACM, 2012

2011

Accelerating Image Analysis For Localization Microscopy With FPGAs

F. Grüll, M. Kirchgessner, R. Kaufmann, M. Hausmann, U. Kebschull.

Heidelberg University and University of Frankfurt

In Proc. International Conference on Field Programmable Logic and Applications, IEEE, 2011

2010

Revisiting Convolution and FFT on Parallel Computation Platforms

H. Fu, R.G. Clapp, O. Lindtjorn

Stanford University

SEG 2010, Denver.